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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Features
* 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) * 300-MHz clock for high bandwidth * 2-Word burst for reducing address bus frequency * Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz * Two input clocks (K and K) for precise DDR timing -- SRAM uses rising edges only * Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches * Echo clocks (CQ and CQ) simplify data capture in high-speed systems * Synchronous internally self-timed writes * 1.8V core power supply with HSTL inputs and outputs * Variable drive HSTL output buffers * Expanded HSTL output voltage (1.4V-VDD) * Available in 165-ball FBGA package (15 x 17 x 1.4 mm) * Offered in both lead-free and non lead-free packages * JTAG 1149.1 compatible test access port * Delay Lock Loop (DLL) for accurate data placement
Functional Description
The CY7C1422V18, CY7C1429AV18, CY7C1423V18, CY7C1424V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports to access the memory array. The Read port has dedicated Data outputs and the Write port has dedicated Data inputs to completely eliminate the need to "turn around' the data bus required with common I/O devices. Access to each port is accomplished using a common address bus. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1422AV18, two 9-bit words in the case of CY7C1429AV18, two 18-bit words in the case of CY7C1423AV18, and two 36-bit words in the case of CY7C1424AV18, that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR-II SIO SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K/K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clock. Writes are conducted with on-chip synchronous self-timed write circuitry.
Configuration
CY7C1422AV18-4M x 8 CY7C1429AV18-4M x 9 CY7C1423AV18-2M x18 CY7C1424AV18-1M x 36
Selection Guide
300 MHz Maximum Operating Frequency Maximum Operating Current 300 825 278 MHz 278 775 250 MHz 250 700 200 MHz 200 600 167 MHz 167 500 Unit MHz mA
Cypress Semiconductor Corporation Document Number: 38-05617 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised June 26, 2006
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Logic Block Diagram (CY7C1422AV18)
D[7:0] 8
Write Data Reg Write Add. Decode Write Data Reg Read Add. Decode
A(20:0)
21
Address Register
K K DOFF R/W VREF LD NWS0 NWS1
2M x 8 Memory Array
2M x 8 Memory Array
CLK Gen.
Control Logic
Read Data Reg. 16 Control Logic 8 Reg. 8 Reg. 8
LD R/W C C
CQ CQ
Reg. 8
8 Q[7:0]
Logic Block Diagram (CY7C1429AV18)
D[8:0] 9
Write Data Reg Write Add. Decode Write Data Reg Read Add. Decode
A(20:0)
21
Address Register
K K DOFF R/W VREF LD BWS0
2M x 9 Memory Array
2M x 9 Memory Array
CLK Gen.
Control Logic
Read Data Reg. 18 Control Logic 9 Reg. 9 Reg. 9
LD R/W C C
CQ CQ
Reg. 9
9 Q[8:0]
Document Number: 38-05617 Rev. *C
Page 2 of 28
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Logic Block Diagram (CY7C1423AV18)
D[17:0] 18
20
Write Add. Decode
K K DOFF R/W VREF LD BWS0 BWS1
1M x 18 Memory Array
1M x 18 Memory Array
Read Add. Decode
A(19:0)
Address Register
Write Data Reg
Write Data Reg
CLK Gen.
Control Logic
Read Data Reg. 36 Control Logic 18 Reg. 18 Reg. 18
LD R/W C C
CQ CQ
Reg. 18
18 Q[17:0]
Logic Block Diagram (CY7C1424AV18)
D[35:0] 36
19
Write Add. Decode
K K DOFF R/W VREF LD BWS[3:0]
512K x 36 152K x 36 Memory Memory Array Array
Read Add. Decode
A(18:0)
Address Register
Write Data Reg
Write Data Reg
CLK Gen.
Control Logic
Read Data Reg. 72 Control Logic 36 Reg. 36 Reg. 36
LD R/W C C
CQ CQ
Reg. 36
36 Q[35:0]
Document Number: 38-05617 Rev. *C
Page 3 of 28
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Pin Configurations 165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1422AV18 (4M x 8)
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
NC/72M NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK
3
A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A
4
R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
A NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS
11
CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
CY7C1429AV18 (4M x 9)
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
NC/72M NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK
3
A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A
4
R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
A NC NC NC D2 NC NC VREF Q1 NC NC NC NC D8 TMS
11
CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC Q8 TDI
Document Number: 38-05617 Rev. *C
Page 4 of 28
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1423AV18 (2M x 18)
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
NC/144M Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK
3
A D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A
4
R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC/288M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
NC/72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS
11
CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
CY7C1424AV18 (1M x 36)
1 A B C D E F G H J K L M N P R
CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO
2
Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK
3
D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A
4
R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A
10
NC/144M Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS
11
CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
NC/288M NC/72M
Document Number: 38-05617 Rev. *C
Page 5 of 28
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Pin Definitions
Pin Name D[x:0] I/O InputSynchronous Pin Description Data Input signals, sampled on the rising edge of K and K clocks during valid Write operations. CY7C1422AV18 - D[7:0] CY7C1429AV18 - D[8:0] CY7C1423AV18 - D[17:0] CY7C1424AV18 - D[35:0] Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and Read/Write direction. All transactions operate on a burst of 2 data (one period of bus activity). Nibble Write Select 0, 1 - active LOW (CY7C1422AV18 only). Sampled on the rising edge of the K and K clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations. Nibbles not written remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written into the device. Byte Write Select 0, 1, 2, and 3 - active LOW. Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1429AV18 - BWS0 controls D[8:0]. CY7C1423AV18 - BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1424AV18 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27] All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the K clock during active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1422AV18, 4M x 9 (2 arrays each of 2M x 9) for CY7C1424AV18, 2M x 18 (two arrays each of 1M x 18) for CY7C1429AV18 and 1M x 36 (2 arrays each of 512K x 36) for CY7C1423AV18. Therefore only 21 address inputs are needed to access the entire memory array of CY7C1422AV18 and CY7C1424AV18, 20 address inputs for CY7C1423AV18, and 19 address inputs for CY7C1424AV18. These inputs are ignored when the appropriate port is deselected. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When Read access is deselected, Q[x:0] are automatically tri-stated. CY7C1422AV18 - Q[7:0] CY7C1429AV18 - Q[8:0] CY7C1423AV18 - Q[17:0] CY7C1424AV18 - Q[35:0] Synchronous Read/Write Input: When LD is LOW, this input designates the access type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and hold times around edge of K. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock for Output Data. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode.
LD
InputSynchronous InputSynchronous
NWS[1:0]
BWS[3:0]
InputSynchronous
A
InputSynchronous
Q[x:0]
OutputSynchronous
R/W
InputSynchronous OutputClock OutputClock InputClock InputClock
C
C
K
K
Document Number: 38-05617 Rev. *C
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Pin Definitions (continued)
Pin Name CQ I/O Echo Clock Pin Description CQ is referenced with respect to C. This is a free-running clock and is synchronized to the Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. CQ is referenced with respect to C. This is a free-running clock and is synchronized to the Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Ground for the device.
CQ
Echo Clock
ZQ
Input
DOFF TDO TCK TDI TMS NC NC/72M NC/144M NC/288M VREF VDD VSS VDDQ
Input Output Input Input Input N/A N/A N/A N/A InputReference Ground
Power Supply Power supply inputs to the core of the device. Power Supply Power supply inputs for the outputs of the device. R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to the Address inputs is stored in the Read address register. Following the next K clock rise the corresponding lowest-order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word is driven onto the Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C or C, or K or K when in single clock mode, for 250-MHz and 200-MHz devices). Read accesses can be initiated on every K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks, C/C (or K/K when in single clock mode). When Read access is deselected, the CY7C1429AV18 will first complete the pending Read transactions. Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the positive output clock (C). Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K), the information presented to D[17:0] is also stored into the Write Data register provided Page 7 of 28
Functional Overview
The CY7C1422AV18, CY7C1424AV18, CY7C1429AV18, CY7C1423AV18 are synchronous pipelined Burst SRAMs equipped with a DDR-II Separate I/O interface. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of the output clocks, C/C (or K/K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks, C/C (or K/K when in single clock mode). All synchronous control (R/W, LD, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clock (K). CY7C1423AV18 is described in the following sections. The same basic descriptions apply to CY7C1422AV18, CY7C1429AV18, and CY7C1424AV18. Read Operations The CY7C1429AV18 is organized internally as two arrays of 1M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting
Document Number: 38-05617 Rev. *C
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
BWS[1:0] are both asserted active. Write accesses can be initiated on every rising edge of input clock (K). Doing so pipelines the data flow so that 18 bits of data are written into the device on every rising edge of both input clocks (K and K). When Write access is deselected, the device will ignore all data inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1429AV18. A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1429AV18 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-on. This function is a strap option and not alterable during device operation. The echo clocks are synchronized to input clocks K/K in this mode. DDR Operation The CY7C1429AV18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double DDR mode of operation. If a Read occurs after a Write cycle, address and data for the Write are stored in registers. The write information must be stored because the SRAM can not perform the last word Write to the array without conflicting with the Read. The data stays in this register until the next Write cycle occurs. On the first Write cycle after the Read(s), the stored data from the earlier Write will be written into the SRAM array. This is called a Posted Write. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 and 350, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the Separate I/O DDR. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. DLL These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be specifically reset in order to lock the DLL to the desired frequency. The DLL will automatically lock 1024 clock cycles after a stable clock is presented.the DLL may be disabled by applying ground to the DOFF pin. For information refer to the application note "DLL Considerations in QDRII/DDRII/QDRII+/DDRII+".
Document Number: 38-05617 Rev. *C
Page 8 of 28
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Application Example[1]
SRAM 1
Vt D R B W B LD R/W W LD R/W S ### ### ZQ Q CQ CQ# C C# K K#
SRAM 4
R = 250 Ohms D B W LD R/W S ###
A
A
ZQ Q CQ CQ# C C# K K#
R = 250 Ohms
BUS MASTER SRAM 1 Input CQ (CPU SRAM 1 Input CQ# SRAM 4 Input CQ or ASIC) SRAM 4 Input CQ#
Source K Source K# Delayed K Delayed K# R R = 50 Ohms Vt = VREF
DATA IN DATA OUT Address LD# R/W# BWS#
R
Vt Vt
Truth Table[2, 3, 4, 5, 6, 7]
Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges. NOP: No Operation Standby: Clock Stopped K L-H LD L R/W L DQ D(A + 0) at K(t + 1) DQ D(A + 1) at K(t + 1)
L-H
L
H
Q(A + 0) at C(t + 1)
Q(A + 1) at C(t + 2)
L-H Stopped
H X
X X
High-Z Previous State
High-Z Previous State
Notes: 1. The above application shows four DDR-II SIO being used. 2. X = "Don't Care," H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device will power-up deselected and the outputs in a tri-state condition. 4. "A" represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst. 5. "t" represents the cycle at which a Read/Write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the "t" clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
Document Number: 38-05617 Rev. *C
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Write Cycle Descriptions (CY7C1422AV18 and CY7C1429AV18) [2, 8]
BWS0/NWS0 L BWS1/NWS1 L K L-H K Comments During the Data portion of a Write sequence: CY7C1422AV18 - both nibbles (D[7:0]) are written into the device, CY7C1423AV18 - both bytes (D[17:0]) are written into the device.
L
L
-
L-H During the Data portion of a Write sequence: CY7C1422AV18 - both nibbles (D[7:0]) are written into the device, CY7C1423AV18 - both bytes (D[17:0]) are written into the device. During the Data portion of a Write sequence: CY7C1422AV18 - only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1423AV18 - only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
L
H
L-H
L
H
-
L-H During the Data portion of a Write sequence: CY7C1422AV18 - only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1423AV18 - only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. - During the Data portion of a Write sequence: CY7C1422AV18 - only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1423AV18 - only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.
H
L
L-H
H
L
-
L-H During the Data portion of a Write sequence: CY7C1422AV18 - only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1423AV18 - only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. - No data is written into the devices during this portion of a Write operation. L-H No data is written into the devices during this portion of a Write operation.
H H
H H
L-H -
Note: 8. Assumes a Write cycle was initiated per the Write Cycle Description Truth Table. BWS0, BWS1 in the case of CY7C1422AV18 and CY7C1429AV18 and also BWS2, BWS3 in the case of CY7C1423AV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
Document Number: 38-05617 Rev. *C
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Write Cycle Descriptions (CY7C1424AV18)[2, 8]
BWS0 L L L L H H H H H H H H BWS1 L L H H L L H H H H H H BWS2 L L H H H H L L H H H H BWS3 L L H H H H H H L L H H K L-H - L-H - L-H - L-H - L-H - L-H - K - Comments During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device.
L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered.
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. - During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. - During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. - No data is written into the device during this portion of a Write operation. L-H No data is written into the device during this portion of a Write operation.
Write Cycle Descriptions (CY7C1429AV18)[2, 8]
BWS0 L L H H K L-H - L-H - K - Comments During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device.
L-H During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. - No data is written into the device during this portion of a Write operation. L-H No data is written into the device during this portion of a Write operation.
Document Number: 38-05617 Rev. *C
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IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port--Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VSS) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the Document Number: 38-05617 Rev. *C TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction Page 12 of 28
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is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the "Update IR" state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST Output Bus Tri-State IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #108. When this scan cell, called the "extest output bus tri-state", is latched into the preload register during the "Update-DR" state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the "Shift-DR" state. During "Update-DR", the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
Document Number: 38-05617 Rev. *C
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TAP Controller State Diagram[9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 1 0 1 1 SELECT IR-SCAN 0
Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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TAP Controller Block Diagram 0 Bypass Register Selection Circuitry TDI 2 Instruction Register 31 30 29 . . 2 1 0 1 0 Selection Circuitry TDO
Identification Register 106 . . . . 2 1 0
Boundary Scan Register
TCK TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[10, 15, 17]
Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and OutputLoad Current GND VI VDD Test Conditions IOH = -2.0 mA IOH = -100 A IOL = 2.0 mA IOL = 100 A 0.65VDD -0.3 -5 Min. 1.4 1.6 0.4 0.2 VDD + 0.3 0.35VDD 5 Max. Unit V V V V V V A
TAP AC Switching Characteristics Over the Operating Range[11,12]
Parameter tTCYC tTF tTH tTL tTMSS tTDIS tCS TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 20 20 5 5 5 Description Min. 50 20 Max. Unit ns MHz ns ns ns ns ns
Set-up Times
Notes: 10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 12. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 38-05617 Rev. *C
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TAP AC Switching Characteristics Over the Operating Range[11,12] (continued)
Parameter Hold Times tTMSH tTDIH tCH tTDOV tTDOX TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 5 5 5 10 ns ns ns ns ns Description Min. Max. Unit
Output Times
TAP Timing and Test Conditions[12]
0.9V 50 TDO Z0 = 50 CL = 20 pF 0V ALL INPUT PULSES 1.8V 0.9V
(a)
GND
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data-In TDI
Test Data-Out TDO
tTDOV tTDOX
Document Number: 38-05617 Rev. *C
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Identification Register Definitions
Value Instruction Field Revision Number (31:29) CY7C1422AV18 000 CY7C1424AV18 000 CY7C1429AV18 000 CY7C1423AV18 000 Description Version number.
Cypress Device ID 11010100010000111 (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) 00000110100
11010100010001111 11010100010010111 11010100010100111 Defines the type of SRAM. 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor. Indicate the presence of an ID register.
1
1
1
1
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 109
Instruction Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Captures the Input/Output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Description
Document Number: 38-05617 Rev. *C
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Boundary Scan Order
Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Bump ID 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B Bit # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bump ID 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H Bit # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Bump ID 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal
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Power-Up Sequence in DDR-II SRAM[13, 14]
DDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power-Up Sequence * Apply power and drive DOFF LOW (All other inputs can be HIGH or LOW) -- Apply VDD before VDDQ -- Apply VDDQ before VREF or at the same time as VREF * After the power and clock (K, K, C, C) are stable take DOFF HIGH * The additional 1024 cycles of clocks are required for the DLL to lock DLL Constraints * DLL uses either K or C clock as its synchronizing input.The input should have low phase jitter, which is specified as tKC Var * The DLL will function at frequencies down to 80 MHz * If the input clock is unstable and the DLL is enabled, then the DLL may lock to an incorrect frequency, causing unstable SRAM behavior
Power-up Waveforms
~ ~
K K
~ ~
Unstable Clock
> 1024 Stable clock
Start Normal Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix High (or tied to VDDQ)
Notes: 13. It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm. 14. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Document Number: 38-05617 Rev. *C
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Maximum Ratings
(Above which the useful life may be impaired.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied .. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +2.9V Supply Voltage on VDDQ Relative to GND ...... -0.5V to +VDD DC Voltage Applied to Outputs in High-Z State .................................... -0.5V to VDDQ + 0.3V DC Input Voltage[15] ............................ -0.5V to VDDQ + 0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage (MIL-STD-883, M 3015)... > 2001V Latch-up Current.................................................... > 200 mA
Operating Range
Range Com'l Ind'l Ambient Temperature 0C to +70C -40C to +85C VDD[16] 1.8 0.1V VDDQ[16] 1.4V to VDD
Electrical Characteristics Over the Operating Range[17]
DC Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[15] Input LOW Voltage[15] Input Load Current Output Leakage Current Input Reference Voltage[20] VDD Operating Supply GND VI VDDQ GND VI VDDQ, Output Disabled Typical Value = 0.75V VDD = Max.,IOUT = 0 mA, 167 MHz f = fMAX = 1/tCYC 200 MHz 250 MHz 278 MHz 300 MHz ISB1 Automatic Power-down Current Max. VDD, Both Ports Deselected, VIN VIH or VIN VIL, f = fMAX = 1/tCYC, Inputs Static 167 MHz 200 MHz 250 MHz 278 MHz 300 MHz AC Input Requirements Over the Operating Range Parameter VIH VIL Description Input HIGH Voltage Input LOW Voltage Test Conditions Min. VREF + 0.2 - Typ. - - Max. - VREF - 0.2 Unit V V Note 18 Note 19 IOH = -0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min. 1.7 1.4 VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 VSS VREF + 0.1 -0.3 -5 -5 0.68 0.75 Typ. 1.8 1.5 Max. 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF - 0.1 5 5 0.95 500 600 700 775 825 220 230 250 260 270 Unit V V V V V V V V A A V mA mA mA mA mA mA mA mA mA mA
Notes: 15. Overshoot: VIH(AC) < VDD+0.85V (Pulse width less than tTCYC/2); Undershoot VIL(AC) > -1.5V (Pulse width less than tTCYC/2). 16. Power-up: Assumes a linear ramp from 0V to VDD(Min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 17. All voltage referenced to ground. 18. Outputs are impedance controlled. IOH = -(VDDQ/2)/(RQ/5) for values of 175 < RQ < 350. 19. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350. 20. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54 VDDQ, whichever is smaller.
Document Number: 38-05617 Rev. *C
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Capacitance[21]
Parameter CIN CCLK CO Description Input Capacitance Clock Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max. 5 4 5 Unit pF pF pF
Thermal Resistance[21]
Parameter JA JC Description Test Conditions 165 FBGA Package 17.2 3.2 Unit C/W C/W Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring Thermal Resistance (Junction to Case) thermal impedance, per EIA/JESD51.
AC Test Loads and Waveforms
VREF = 0.75V VREF OUTPUT Device Under Test Z0 = 50 RL = 50 VREF = 0.75V 0.75V VREF OUTPUT Device Under Test ZQ 5 pF 0.25V Slew Rate = 2 V/ns 0.75V R = 50 ALL INPUT PULSES 1.25V 0.75V
[22]
ZQ
RQ = 250
(a)
RQ = 250 (b)
Notes: 21. Tested initially and after any design or process change that may affect these parameters. 22. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
Document Number: 38-05617 Rev. *C
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Switching Characteristics Over the Operating Range[22,23]
Cypress Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tKHKH tKHKL tKLKH tKHKH 300 MHz Description VDD(Typical) to the first Access[24] K Clock and C Clock Cycle Time Input Clock (K/K and C/C) HIGH Input Clock (K/K and C/C) LOW K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) Address Set-up to K Clock Rise Control Set-up to K Clock Rise (LD, R/W) Double Data Rate Control Set-up to Clock (K, K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Set-up to Clock (K/K) Rise Address Hold after K Clock Rise Control Hold after K Clock Rise (LD, R/W) Double Data Rate Control Hold after Clock (K, K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Hold after Clock (K/K) Rise 1 3.30 1.32 1.32 1.49 - 278 MHz 1 - 250 MHz 1 4.0 1.6 1.6 1.8 6.3 - - - 200 MHz 1 5.0 2.0 2.0 2.2 7.9 - - - 167 MHz Unit ms 8.4 - - - ns ns ns ns 1 6.0 2.4 2.4 2.7 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
5.25 3.60 5.25 - - - 1.4 1.4 1.6 - - -
tKHCH
tKHCH
0.00
1.45 0.00 1.55
0.0
1.8
0.0
2.2
0.0
2.7
ns
Set-up Times tSA tSC tSCDDR tAVKH tIVKH tIVKH 0.4 0.4 0.3 - - - 0.4 0.4 0.3 - - - 0.5 0.5 0.35 - - - 0.6 0.6 0.4 - - - 0.7 0.7 0.5 - - - ns ns ns
tSD[25]
tDVKH
0.3
-
0.3
-
0.35
-
0.4
-
0.5
-
ns
Hold Times tHA tHC tHCDDR tKHAX tKHIX tKHIX 0.4 0.4 0.3 - - - 0.4 0.4 0.3 - - - 0.5 0.5 0.35 - - - 0.6 0.6 0.4 - - - 0.7 0.7 0.5 - - - ns ns ns
tHD
tKHDX
0.3
-
0.3
-
0.35
-
0.4
-
0.5
-
ns
Notes: 23. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range. 24. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation can be initiated. 25. For D2 data signal on CY7C1429AV18 device, tSD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
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Switching Characteristics Over the Operating Range[22,23] (continued)
Cypress Consortium Parameter Parameter tCO tCHQV 300 MHz Description C/C Clock Rise (or K/K in single clock mode) to Data Valid Data Output Hold after Output C/C Clock Rise (Active to Active) C/C Clock Rise to Echo Clock Valid - 0.45 278 MHz - 0.45 250 MHz - 0.45 200 MHz - 0.45 167 MHz Unit ns - 0.50 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tDOH
tCHQX
-0.45
-
-0.45
-
-0.45
-
-0.45
-
-0.50
-
ns
tCCQO tCQOH tCQD tCQDOH tCHZ
tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ
-
0.45 - 0.27 - 0.45
- -0.45 - -0.27 -
0.45 - 0.27 - 0.45
- -0.45 - -0.30 -
0.45 - 0.30 - 0.45
- -0.45 - -0.35 -
0.45 - 0.35 - 0.45
- -0.50 - -0.40 -
0.50 - 0.40 - 0.50
ns ns ns ns ns
Echo Clock Hold after C/C -0.45 Clock Rise Echo Clock High to Data Change Echo Clock High to Data Change Clock (C/C) Rise to High-Z (Active to High-Z)[26, 27] Clock (C/C) Rise to Low-Z[26, 27] Clock Phase Jitter DLL Lock Time (K, C) K Static to DLL Reset - -0.27 -
tCLZ
tCHQX1
-0.45
-
-0.45
-
-0.45
-
-0.45
-
-0.50
-
ns
DLL Timing tKC Var tKC lock tKC Reset tKC Var tKC lock tKC Reset - 1024 30 0.20 - - - 1024 30 0.20 - - - 1024 30 0.20 - - 1024 30 0.20 - - 1024 30 0.20 - ns Cycles ns
Notes: 26. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 100 mV from steady-state voltage. 27. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document Number: 38-05617 Rev. *C
Page 23 of 28
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Switching Waveforms[28, 29, 30]
NOP 1
K tKH K LD t SC R/W A tSA A0 tHA A1 A2 tHD tSD D D20 D21 A3 A4 tHD tSD D30 D31 tHC tKL tCYC tKHKH
READ (burst of 2) 2
READ (burst of 2) 3
WRITE (burst of 2) 4
WRITE (burst of 2) 5
READ (burst of 2) 6
NOP 7 8
Q t KHCH t KHCH tCO C t CLZ
Q00
Q01 tCQD
Q10
Q11 tDOH t CHZ
Q40
Q41
tCQDOH
tKH C# tCQOH CQ tCQOH CQ# tCCQO tCCQO
tKL
tCYC
tKHKH
DON'T CARE
UNDEFINED
Notes: 28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1. 29. Output are disabled (High-Z) one clock cycle after a NOP. 30. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram
Document Number: 38-05617 Rev. *C
Page 24 of 28
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1422AV18-167BZC CY7C1429AV18-167BZC CY7C1423AV18-167BZC CY7C1424AV18-167BZC CY7C1422AV18-167BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1429AV18-167BZXC CY7C1423AV18-167BZXC CY7C1424AV18-167BZXC CY7C1422AV18-167BZI CY7C1429AV18-167BZI CY7C1423AV18-167BZI CY7C1424AV18-167BZI CY7C1422AV18-167BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1429AV18-167BZXI CY7C1423AV18-167BZXI CY7C1424AV18-167BZXI 200 CY7C1422AV18-200BZC CY7C1429AV18-200BZC CY7C1423AV18-200BZC CY7C1424AV18-200BZC CY7C1422AV18-200BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1429AV18-200BZXC CY7C1423AV18-200BZXC CY7C1424AV18-200BZXC CY7C1422AV18-200BZI CY7C1429AV18-200BZI CY7C1423AV18-200BZI CY7C1424AV18-200BZI CY7C1422AV18-200BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1429AV18-200BZXI CY7C1423AV18-200BZXI CY7C1424AV18-200BZXI 250 CY7C1422AV18-250BZC CY7C1429AV18-250BZC CY7C1423AV18-250BZC CY7C1424AV18-250BZC CY7C1422AV18-250BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1429AV18-250BZXC CY7C1423AV18-250BZXC CY7C1424AV18-250BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial Package Diagram Package Type Operating Range Commercial
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Document Number: 38-05617 Rev. *C
Page 25 of 28
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Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 250 Ordering Code CY7C1422AV18-250BZI CY7C1429AV18-250BZI CY7C1423AV18-250BZI CY7C1424AV18-250BZI CY7C1422AV18-250BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1429AV18-250BZXI CY7C1423AV18-250BZXI CY7C1424AV18-250BZXI 278 CY7C1422AV18-278BZC CY7C1429AV18-278BZC CY7C1423AV18-278BZC CY7C1424AV18-278BZC CY7C1422AV18-278BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1429AV18-278BZXC CY7C1423AV18-278BZXC CY7C1424AV18-278BZXC CY7C1422AV18-278BZI CY7C1429AV18-278BZI CY7C1423AV18-278BZI CY7C1424AV18-278BZI CY7C1422AV18-278BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1429AV18-278BZXI CY7C1423AV18-278BZXI CY7C1424AV18-278BZXI 300 CY7C1422AV18-300BZC CY7C1429AV18-300BZC CY7C1423AV18-300BZC CY7C1424AV18-300BZC CY7C1422AV18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1429AV18-300BZXC CY7C1423AV18-300BZXC CY7C1424AV18-300BZXC CY7C1422AV18-300BZI CY7C1429AV18-300BZI CY7C1423AV18-300BZI CY7C1424AV18-300BZI CY7C1422AV18-300BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1429AV18-300BZXI CY7C1423AV18-300BZXI CY7C1424AV18-300BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial Package Diagram Package Type Operating Range Industrial
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Document Number: 38-05617 Rev. *C
Page 26 of 28
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
Package Diagram
165-ball FBGA (15 x 17 x 1.40 mm) (51-85195)
51-85195-*A
QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document Number: 38-05617 Rev. *C
Page 27 of 28
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Document History Page
Document Title: CY7C1422AV18/CY7C1429AV18/CY7C1423AV18/CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number: 38-05617 REV. ** *A ECN No. 247331 326519 Issue Date See ECN See ECN Orig. of Change SYT SYT New Data Sheet Removed CY7C1429AV18 from the title Included 300 MHz Speed grade Replaced TBDs with their respective values for IDD and ISB1 Added Industrial temperature Replaced the TBDs on the Thermal Characteristics Table to JA = 17.2C/W and JC = 3.2C/W Replaced TBDs in the Capacitance Table to their respective values for the 165 FBGA Package Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS TRI-STATE on Page 17 Added lead-free Product Information Updated the Ordering Information by Shading and Unshading MPNs as per availability Converted from preliminary to final Added CY7C1429AV18 part number to title Added 278-MHz speed Bin Changed C, C Description in Feature Section and Pin Description Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Added Power-up sequence and Wave form on page# 18 Added Footnote# 13, 14, 15 on page# 18 Replaced Three-state with Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 19 Modified the IDD and ISB values Modified test condition in Footnote #17 on page# 19 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD to Alternately, this pin can be connected directly to VDDQ Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform Changed the Maximum rating of Ambient Temperature with Power Applied from -10C to +85C to -55C to +125C Added additional notes in the AC parameter section Modified AC Switching Waveform Updated the Typo in the AC Switching Characteristics Table Updated the Ordering Information Table Description of Change
*B
413953
See ECN
NXR
*C
468029
See ECN
NXR
Document Number: 38-05617 Rev. *C
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